A time divisional electronic switching unit transmits voices and data to line interface units after time-multiplexing them. The time divisional method can utilize more efficiently in space than the conventional method in which physical wires and patterns printed on printed wiring boards are provided one to one to each line interface unit in a space divisional manner. However, since signals of a plural number of line interface units correspond to a physical signal line in the above described time-multiplexing method, a strobe signal is required to communicate where in the timing in the time-multiplexed highway the necessary data are located and the timing that the data to be transmitted should be positioned so that information is correctly transmitted to and collected from a desired line interface unit.
For example, when voice data and digital data are transmitted at the rate of 256 Kb/s per line, and the number of lines to be controlled is 128, 128 lines of 256 Kb/s data lines are required when a time-multiplexing system is not employed. However, only sixteen data lines for transmitting data at the rate of 2.048 Mb/s are required because eight lines can be time multiplexed. Furthermore, fewer signal lines are required if the data lines are more efficiently used.
Thus, since the information for eight lines for example, is multiplexed into one signal line, a signal is required to notify each of the line interface units of the timing of the data transmitted to each line. In a circuit pack containing a common circuit for 8 lines, one signal line is provided for each highway. This is normally referred to as a frame synchronous signal (FCK). In response to this signal, each necessary timing is generated by an internal counter of a control circuit commonly provided for eight lines in synchronization with the system common unit, and data is obtained by and output from each line. Since a number of signal lines (at least eight lines) indicating various timings are required in between the common circuit for lines and the line interface units, this is applicable to the system in which each of the lines to be multiplexed to a highways is housed in one circuit pack.
FIG. 1 shows the configuration of the conventional switching unit accommodating 16 highways. A system common unit CMC outputs highways H1-H16, a frame synchronous signal FCK, and a clock signal CLOCK. Similary, the system common unit receives 16 highways from the line circuit pack. Circuit packs PCB1-PCB16 are provided corresponding to highways H1-H16. For example, highway H1 is associated with circuit pack PCB1. Circuit pack PCB1 comprises a common unit for lines comprising a controller CTRX and a timing generator TGX, and line interface circuits L1-L8 each of which connect to a telephone line and a common highway H1. The common unit for lines generates a clock by which corresponding data are received from the highway to line interface units L1-L8, and vise versa data is output to the highway. Using the clock, the line interface units multiplex data into the highway.
FIG. 2 is a timing chart of the conventional method. In single-phase highways in which all the highways are synchronized in one phase, an 8-phase synchronous signal is required for highways H1-H16. That is, in response to a frame synchronous signal FCK, 8-synchronous signals are necessary for multiplexing. Therefore, if a single-line circuit pack is realized, an independent clock must be generated for each of the lines C1-CB.
FIG. 3 shows the circuit of a controller CTRX, and FIG. 4 shows the circuit of a timing generator TGX. The counter of the controller CTRX comprises a counter preset by a frame synchronous signal and started by a clock signal CLOCK. Its count outputs BCA-BCC and TSCA-TSCR are applied to a timing generator, decoded by a decoder comprising OR gates OR1-OR3, and received by a flipflop in synchronizing with the clock signal CLOCK when a specific value "0" is indicated. Since eight decoders are provided, inverters IX1-IX3 are inserted after determining according to each of the decoding values as to whether or not the outputs of the counter TSCC, TSCD, and SSCE, to be applied to each decoder to obtain an 8-phase clock, should be inverted. The 8-phase clock can be thus generated. FIG. 4 shows that the timing signal is output when all of TSCC, TSCD, and TSCE indicate "1". The absence or presence of the inverter generates an 8-phase clock through eight circuits.
When the system comprises a single-line circuit pack, the selection of a line is not determined at the manufacturing of the circuit pack. Therefore, to apply to operation of the single-line circuit pack, a circuit for generating eight types of phases must be incorporated for all channels. Otherwise, each line interface unit must be provided with a controller and a timing generator for one line as shown in FIG. 5, which are similar to those in the above described common unit for lines.
If the 16 highways have the same phase, 8 synchronous signals must be provided per 128 lines. However, if the 256 kb/s of a signal to a line coordinating unit comprises four 64 Kb/s parts, more synchronous signal lines are required. Four 64 Kb/s parts are, for example, B1, B2, and D for the ISDN, in addition to a control signal.
In this case, 32 (8.times.4) synchronous signals are required for 128 lines.
FIG. 6 is a timing chart of a 4-phase highway. 4 time slots are assigned to one line, and H1-H4 are shifted in phase. Each of the 4 phases has a different phase configuration depending on the data in B1, B2, D, and C (control data).
If the four 64 Kb/s parts corresponds to B1, B2, and D for the ISDN, and a control signal, four phases are normally supplied for convenience in designing the system common unit. In this case, 32 (4.times.8) synchronous signals per 128 lines are required.
FIG. 7 shows a timing chart when data is transmitted on one highway divided into four phases. FIG. 7 shows that, with respect to data B1, B2, C and D shown in FIG. 6, data at which synchronous timing (1-32) is transmitted.
The system provided with a common unit for lines and the line interface circuits mounted on a single circuit pack often causes a problem in maintenance. That is, since the system comprises more than one line in a circuit pack, one defective line affects the other lines, for example, by requiring the replacement of all lines simultaneously and during the replacement other circuits can not be used. Therefore, lately, a method of implementing one line in one circuit pack (a single-line circuit pack method) has become more popular than the above described method of implementing a plurality of lines in one circuit pack.
In the single-line circuit pack method, however, the conventional technique cannot be applied when it is desired to have the minimum number of signal lines incorporated through a simple connection. This is the case for example, when each of the line interface circuits L1-L8, which are independent from one another, must be provided with controllers CTRY and timing generators TGY corresponding to the common unit for lines as shown in FIG. 5.
Thus, providing a circuit pack corresponding to a single line results in effective maintenance. However, in spite of the reduction of the number of signals by time multiplexed highway technique, the number of control signal lines and clock signal lines increases and the wiring in the whole system becomes complicated.